1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory (DRAM) having a self-refresh function.
2. Description of the Related Art
Recently, information processing devices having improved functions and high performances have begun to require dynamic semiconductor memories, such as DRAMs, that have large capacity and consume little power. Suitable devices have been developed as semiconductor memories for these information processing devices.
DRAMs are semiconductor memories having capacitors that accumulate charges depending on the data of ("1" and "0") that they are required to store. The DRAMs, unlike SRAMs (Static Random Access Memories), have no data storage mechanism using flip-flop circuits. One typical DRAM configuration is a one-transistor memory device configuration in which each one-bit memory cell is composed of two elements, i.e., a MOS transistor and a capacitor. If each memory cell of the DRAM is left as it is after data is written thereto, the data will disappear as time passes because of leekage currents. Accordingly, the DRAM requires a refresh operation to be carried out at predetermined intervals, to read stored data from the memory and to rewrite the data to the memory.
Nevertheless, each memory cell of the DRAMs occupies a small area, so that the DRAMs are economical because of their large data storage capacities. The DRAMs, therefore, are widely used as main memories in a variety of computers including general purpose large-sized computers and personal computers. Note, recent DRAMs used for portable personal computers have a self-refresh mode for keeping data in memory cells with no external control signals. Namely, recently, DRAMs having the self-refresh function for automatically refreshing memory cells have been proposed. For example, when the DRAMs are applied to a note type personal computer, which is driven by a battery, the consumption of power by the personal computer must be small. Therefore, the self-refresh mode of the DRAMs must be carried out at low power consumption.
In the prior art, Japanese Unexamined Patent Publication (Kokai) No. 3-149867 (Jun. 26, 1991) corresponding to U.S. patent application Ser. No. 07/957,055, now U.S. Pat. No. 5,309,040 issued May 3, 1994, and EP-A1-454859, which discloses a one-chip memory having a step-down circuit, has been published. Further, in the prior art, the following documents have been published: Nogami et al., "1-Mb virtually static RAM", IEEE J. Solid-State Circuits., vol. SC-21, 662. 1986; Yoshioka et al., "4Mb pseudo/virtually SRAM", in 1987 ISSCC Dig. Tech. Papers, 20. 1987; and Konishi et al., "A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode", IEEE J. Solid-State Circuits, vol. 25, 1112. 1990.